1) Field of the Invention
The present invention relates to a technology to reduce amount of timing reproduction data to enhance information recording density in an information recording/reading apparatus.
2) Description of the Related Art
An information recording/reading apparatus such as a magnetic disk drive is required to read out information from a recording medium at the same timing as that for recording the information in the recording medium. Specifically, the timings for recording and reading the information are required to have the same phase and cycle.
In the magnetic disk drive, a data reading section that reproduces the information recorded in the recording medium includes a timing reproducing mechanism for reproducing the timing that is used for recording the information (see, for example, Japanese Patent Application No. 2002-11018). FIG. 8 is a block diagram of a data reading unit including a conventional timing reproducing unit.
A head-read signal output from a head is converted into a digital signal through a variable gain amplifier (VGA) 50, a continuous time filter (CTF) 52 serving as a low-pass filter, and an analog-to-digital converter (ADC) 54. It is then subjected to waveform equalization through a finite impulse response (FIR) filter 56, and written in a buffer 62 as equalized signal data on a sector basis.
A gain controller 58 is employed to control gain of the VGA 50 to correct the head-read signal to a constant amplitude. The ADC 54 samples the head-read signal for generating a discrete signal using a clock from a clock generator 60 to convert it into a digital signal. The sampling clock from the clock generator 60 is a fixed clock that is not synchronous with the head-read signal.
When writing of a preamble at the leading potion of sector data is finished, reading of the sector data stored in the buffer 62 is started in order from leading data, and equalized signal data x is input to an FIR interpolating filter 64.
The buffer 62 delays the signal data output from the FIR filter 56 by a length of the preamble and supplies the delayed data to the FIR interpolating filter 64. In this case, the preamble corresponds to timing reproduction data for reproducing the recording timing, being cyclic waveform data.
The FIR interpolating filter 64, a Viterbi decoder 66, an error detector 76, a loop filter 74, and a digital accumulator 65 are looped to constitute a digital Phase Locked Loop (PLL). The digital PLL employs the preamble contained in the signal data delayed by the buffer 62 for frequency extraction and phase extraction.
The FIR interpolating filter 64 acts as a re-sampler for sampling in synchronization with a symbol rate. The Viterbi decoder 66 determines a correct signal y′ using a Viterbi algorithm on the equalized signal y. A run length limited (RLL) decoder 68 outputs a RLL-decoded signal to a hard disk controller.
The error detector 76 detects a phase error between the output signal y from the FIR interpolating filter 64 and the correct signal y′ determined by the Viterbi decoder 66. The detected phase error is integrated in the loop filter 74 and further integrated in the digital accumulator 65 to adjust the FIR interpolating filter 64 to match the fixed-clock-based sampling rate with the original symbol rate timing.
A phase offset detector 70 detects a phase offset (initial phase error) from the input preamble at the leading portion of the sector data output from the ADC 54, and presets the detected phase offset in the loop filter 74.
A frequency offset detector 72 detects a frequency offset (initial frequency error) from the input preamble at the leading portion of the sector data output from the ADC 54, and presets the detected frequency offset in the loop filter 74.
After the phase offset detector 70 presets the phase offset in the loop filter 74 and the frequency offset detector 72 presets the frequency offset in the loop filter 74, the FIR interpolating filter 64 starts reading of the sector data written in the buffer 62 in order from the leading portion thereof.
In synchronization with reading of the sector data out of the buffer 62, the digital PLL, including the error detector 76, the loop filter 74, the digital accumulator 65, and the FIR interpolating filter 64, operates for phase extraction and frequency extraction with respect to the preamble. Then, timing reproduction is performed with respect to the user data that follows the preamble such that the timing of the sampling signal at the sampling rate follows the timing of the correct clock at the symbol rate.
In order to detect the frequency offset accurately using the frequency offset detector 72, the preamble or timing reproduction data is required to have at least a predetermined length. Lengthening of timing reproduction data, however, causes a problem associated with decrease of the information recording area.